1. Field of the Invention
The present invention generally relates to comparators. More specifically, the present invention improves the bit-error rate of high-speed comparators that operate at low supply voltages.
2. Related Art
A comparator is designed to compare an input signal to a known reference level. The input signal can be an input voltage or an input current. Correspondingly, the known reference level can be a known voltage reference level or a known current reference level. Typically, the comparator is designed to output a logic “1” at the end of a clock cycle, when the input signal exceeds the known reference level, and to output a logic “0” at the end of the clock cycle, when the input signal is below the known reference signal. Alternatively, the comparator can be designed to operate in a converse manner. That is, the comparator can output a logic “0” at the end of the clock cycle, when the input signal exceeds the known reference level, and to output a logic “1” at the end of a clock cycle when the input signal is below the known reference level.
Comparators are basic building blocks of an Analog-to-Digital Converter (ADC). Transistors arranged to provide positive feedback are typically used to implement the comparator. Some ADC architectures, such as flash, folding and subranging ADCs, require a large number of comparators. The large number of comparators used in these ADC architectures drives the need to make the comparators capable of operating with low power supply voltages. A low power comparator reduces overall power consumption and therefore allows an ADC architecture to incorporate more comparators into its design.
Comparators are often required to operate using small input signals. Typically, the comparator can generate an output (i.e., a logic “1” or a logic “0”) more quickly when provided with a large input signal. Consequently, with a small input signal, the comparator needs more time to generate the output. A bit-error may result if the comparator does not generate the output by the end of the clock cycle. With conventional ADC architectures, clock cycles are becoming shorter and input signals are becoming smaller. Accordingly, comparators that operate at high speeds, from low supply voltages, and with low bit-error rates (BERs) are desired.
The BER of the comparator strongly depends on the bias currents of the transistors used in the comparator. The bias currents within the comparator are limited by the supply voltage of the comparator. One technique for achieving a low BER without increasing the supply voltage or extending the clock cycle of the comparator involves lowering the threshold voltage of the transistors. Fabrication of low threshold voltage transistors, however, is expensive. Further, the power consumption of an “off” transistor that has a lowered threshold voltage may become high enough to be impractical.
Another technique for achieving a low BER is to implement the comparator using thick-oxide transistors that are operated from an input/output (I/O) supply voltage. The I/O power supply is often significantly higher than the power supply provided to core transistors. Thick-oxide transistors, however, require more area within an ADC, because their minimum length is greater than that of the core transistors. Further, thick-oxide transistors have a lower transconductance for the same bias current, which has a detrimental effect on the BER of the comparator. Finally, because thick-oxide transistors are operated from the higher I/O power supply, the power consumption of the comparator will increase significantly.